Post - Mapping Transformations for Low - Power Synthesis yRajendran Panda and Farid

نویسندگان

  • Rajendran Panda
  • Farid N. Najm
چکیده

We propose a logic synthesis system that includes power optimization after technology mapping. Our approach is unique in that our post-mapping logic transformations take into account information on circuit delay, capacitance, arrival times, glitches, etc, to provide much better accuracy than previously proposed technology-independent power optimization methods. By changing connections in a mapped circuit that was earlier restructured for lower switching activity, we achieve power improvements up to 59% in case of area-optimized circuits and 38% in delay-optimized circuits. The average power reduction is 15% and 13% for the above cases respectively, with reductions also in area and delay. The transformations are based on the transition density model of circuit switching activity and the concept of permissible logic functions. The techniques presented here are applicable equally well to both synchronous and asynchronous circuits. The power measurements are done under a general delay model.

برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

منابع مشابه

Post-Mapping Transformations for Low-Power Synthesis y

We propose a logic synthesis system that includes power optimization after technology mapping. Our approach is unique in that our post-mapping logic transformations take into account information on circuit delay, capacitance, arrival times, glitches, etc, to provide much better accuracy than previously proposed technology-independent power optimization methods. By changing connections in a mapp...

متن کامل

Technology Decomposition for Low-Power Synthesisy

Technology decomposition and technology mapping are two potential stages for minimizing circuit power during logic synthesis. Since power in CMOS circuits is directly dependent on the extent of circuit switching activity, we present a novel procedure to construct a low-activity circuit structure in the technology decomposition stage. This would result in low-power circuits when mapped. The algo...

متن کامل

Implication-Based Gate-level Synthesis for Low-Power Topics: Technology-Independent, Combinational Logic Synthesis and Optimization

The paper presents a new logic optimization method of multi-level combinational CMOS circuits, which minimizes area and power. Present methods to reduce power on logic circuits apply functional methods like logic factorization on the Boolean networks. The method described here uses Boolean transformations that exploit implications at the gate-level based on both controllability and observabil-i...

متن کامل

Low-power memory mapping through reducing address bus activity

Arrays in behavioral specifications that are too large to fit into on-chip registers are usually mapped to off-chip memories during behavioral synthesis. We address the problem of system power reduction through transition count minimization on the memory address bus when these arrays are accessed from memory. We exploit regularity and spatial locality in the memory accesses and determine the ma...

متن کامل

Behavioral Array Mapping into Multiport Memories Targeting Low Power

Off-chip memories are typically used during behavioral synthesis to store large arrays that do not fit into on-chip registers. An important power-optimization problem that arises in this context is the minimizationof signal transitions on the off-chip buses connecting the ASIC and the memory. We address the problem of system power reduction through transition count minimization on the multiport...

متن کامل

ذخیره در منابع من


  با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید

برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

عنوان ژورنال:

دوره   شماره 

صفحات  -

تاریخ انتشار 1995